In systems that include semiconductor memory devices, power consumed during data interface is proportional to a clock frequency used for the data interface. Accordingly, power consumed during a high-speed data interface is greater than that consumed during a low-speed data interface. Also, as the transmission rate of an input/output (I/O) interface increases, skew caused by different delays occurring in channels between the interfacing semiconductor devices also increases. Accordingly, per pin deskewing is necessary for pins corresponding to the respective channels in the semiconductor devices.
In order to compensate for skew, clock and data recovery (CDR) may be performed. In order to accomplish high-speed data transmission, differential signaling is more advantageous than single ended signaling, which is sensitive to supply noise, cross-talk and inter-symbol interface, for example. Generally, CDR and differential signaling may be used together for a high-speed data interface.